
2002 Microchip Technology Inc.
Preliminary
DS30485A-page 219
PIC18FXX39
ANDWF
AND W with f
Syntax:
[ label ] ANDWF
f [,d [,a]
Operands:
0
≤ f ≤ 255
d
∈ [0,1]
a
∈ [0,1]
Operation:
(W) .AND. (f)
→ dest
Status Affected:
N,Z
Encoding:
0001
01da
ffff
Description:
The contents of W are AND’ed with
register 'f'. If 'd' is 0, the result is
stored in W. If 'd' is 1, the result is
stored back in register 'f' (default). If
‘a’ is 0, the Access Bank will be
selected. If ‘a’ is 1, the BSR will not
be overridden (default).
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register 'f'
Process
Data
Write to
destination
Example:
ANDWF
REG,
0, 0
Before Instruction
W
=
0x17
REG
=
0xC2
After Instruction
W
=
0x02
REG
=
0xC2
BC
Branch if Carry
Syntax:
[ label ] BC n
Operands:
-128
≤ n ≤ 127
Operation:
if carry bit is ‘1’
(PC) + 2 + 2n
→ PC
Status Affected:
None
Encoding:
1110
0010
nnnn
Description:
If the Carry bit is ‘1’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will
have incremented to fetch the next
instruction, the new address will be
PC+2+2n. This instruction is then
a two-cycle instruction.
Words:
1
Cycles:
1(2)
Q Cycle Activity:
If Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
Write to PC
No
operation
No
operation
No
operation
No
operation
If No Jump:
Q1
Q2
Q3
Q4
Decode
Read literal
'n'
Process
Data
No
operation
Example:
HERE
BC
5
Before Instruction
PC
=
address (HERE)
After Instruction
If Carry
=
1;
PC
=
address (HERE+12)
If Carry
=
0;
PC
=
address (HERE+2)